1. Field of the Invention
The present invention relates generally a system receiver, and more particularly, to a receiver having an equalizer and a related method of operation.
2. Description of the Related Art
Serializer and deserializer circuits (collectively or singularly SerDes) are commonly used in data communication systems. SerDes generally include a preamplifier, an equalizer, a sampler, and a clock data recovery (CDR) circuit.
SerDes recover the transmission frequency of a received data (i.e., a recovered clock signal) using the CDR circuit. The constituent sampler circuit is then operated in relation to the recovered clock signal. Accordingly, a receiver incorporating the SerDes is able to continuously receive data transmitted by a corresponding transmitter operating at a transmission frequency different from a reference clock in the receiver.
When transmitting data at high speed through a transmission line (e.g., a metal wire, or trace and associated drivers, latches, terminal, etc.), inter symbol interference (ISI) may occur due to noise associated with the transmission line. Because of ISI, the amplitude and/or phase of data bits being communicated may become highly distorted leading to bit errors in data received by the receiver. As a transmission line lengthens and as data transmission speed increases, the amplitude and/or phase of data bits in a received signal at the receiver tend to become more distorted.
Reception data integrity is always an issue in systems including SerDes, since such circuits include an interface receiving serial data having a certain amount of jitter, a particular noise component associated with the data. Data distortion is routinely measured with instrumentation showing a data “eye” having a shape and size indicative of data integrity (i.e., the manifest distinction between 1's and 0's in the data stream). Data integrity as a function of the recovered clock signal is critical to the proper operation of flip-flops or latches functionally incorporated with the receiver sampler.
The preamplifier of SerDes amplifies the voltage of the received data, and the equalizer equalizes the received data to reduce jitter in the received data, and then outputs the equalized data to the sampler.
The equalizer includes at least one control bit used to control the equalization function applied to the received data in relation to the jitter associated with the received data. That is, the equalizer may turn ON/OFF an equalizing function according to the jitter property of received data. In a case where the measured eye size of received data is small, the equalizer may increase the strength of the applied equalization function. In contrast, a large eye size may result in a reduction of applied equalization function. Thus, an adaptive equalizer may be operated to maximize eye size for the received data (i.e., improve data integrity).
However, many conventional receivers having an adaptive equalizer adjust the strength of the equalization function (hereafter, “equalizing strength”) in the blind, or without regard to the actual integrity of the received data. Due to this, when ISI jitter of received data are great, the equalizing strength may be incorrectly adjusted or applied. That is, an equalizer applying an improper equalizing strength may equalize intended data of ‘1010’ into erroneous data of ‘1111’ or ‘0000’.